(On) The Impact of the Micro- architecture on Countermeasures against Side-Channel Attacks

Although “Masking” comes with formal security guarantees against side-channel attacks, physical non-idealities (e.g., state-transitions of registers) potentially reduce the proven security.

In the context of software implementations, the physical non-idealities of a CPU – thus, the CPU’ side-channel behaviour – strictly depend on the microarchitectural choices underlying the CPU.

Due to such microarchitectural non-idealities (or “effects”), researchers are actively studying approaches to deliver practically secure masked software implementations.

In this seminar, we present two orthogonal methodologies contributing to the current research efforts.

The first methodology targets a microarchitecture-dependent approach, and evaluates the use of optimising compilers to mitigate transition-based leakages in an automated manner.

The second methodology targets an microarchitecture-independent approach, and evaluates the use of masking schemes with different algebraic structures to mitigate the side-channel leakage of different microarchitectural effects.

We conclude the presentation with a summary of the current limitations research perspectives of the two presented approaches.